How combining cobalt and copper could improve chip yields, boost performance

When we talk about semiconductor performance scaling, we often talk about process nodes like 20nm or 14nm FinFET. The concept of a node is a shorthand that combines a number of advances in various metrics and declares that these improvements, collectively, represent a new manufacturing level. One of the most important areas is interconnect scaling. The term refers to the tiny copper wires that connect the chip to itself internally. Interconnects have proven increasingly difficult to scale as die sizes have shrunk, but a new technology from Applied Materials combines copper with a cobalt sheath and dramatically improves yield and reliability in the process.

There are multiple problems with scaling copper interconnects down to ever-smaller sizes. First, the total current that the wire has to carry isn’t scaling proportionally anymore, which means that a tiny wire has to carry more electricity (relative to its own size) with every passing generation. Second, as the wires get smaller, the chance of a defect rises — it becomes increasingly hard to ensure that enough copper makes it into the gap to prevent the formation of a void (more on this in a moment).
The problem is that as chip complexity skyrockets, the number of copper interconnects rises as well — even as the ability of the chip to tolerate defects falls.

The slide above is from an Nvidia presentation in 2011; Applied Materials extrapolated the 20nm line. What the graph shows is that a 130nm GPU could tolerate almost one defective part (a bad via) per million and yield rates would suffer by just 10%. By 20nm, a defect rate of one defective part per billion would cause a failure rate of nearly 30%. As of 2011, Nvidia was hedging its bets by including multiple via’s on 75% of a GPU — meaning it had a secondary path ready to go if the primary failed. Unfortunately, this redundant approach cannot scale indefinitely, adding copper wire to the die drastically increases cost and complexity. So, how do you solve this problem?
You add cobalt.
The first slide below shows copper fill at the 28nm node and again at 20nm. Note that the amount of tantalum nitrate has halved, the amount of copper used has nearly halved, and the gap is so small that the risk of forming a void (shown as poor copper fill) is much higher.

Laying down a liner of cobalt before the copper deposition state, however, dramatically improves the copper’s fill performance at smaller geometries. This leads to far fewer voids and better overall performance.

Engineers have known about this problem for years and have created a number of proposed solutions for it, but virtually all of these have required trading some of copper’s excellent electrical characteristics for lower defect rates. Increasing electrical resistance inside the core when chips are under enormous pressure already isn’t attractive. Cobalt appears to solve this problem — and according to Applied Materials, the technology can be integrated into its Endura platform rather than requiring a completely different set of tools. This isn’t a pie-in-the-sky technology; Applied Materials has already shipped 75 chambers in the past two years and qualified multiple customers.
The video below shows how the cobalt is deployed and integrated into copper manufacturing.

What does it mean for the future of the industry?

After focusing on a small (but vital) change like this, it’s important to pull back and look at the bigger picture. Interconnect scaling is one of the most difficult problems facing modern semiconductors — smaller wires cannot carry an ever-greater amount of current, and voltage isn’t falling proportionally relative to transistor size any longer. Is this going to lead to faster chips? Not directly — not in the sense that you can adopt this method and then increase clock rates by 20%, no.
It does, however, improve reliability and hopefully allows companies to avoid continuing to scale up the number of vias in a chip (thereby increasing complexity and cost) or avoiding the problem by adapting technology that hurts copper’s overall performance and necessitates lower clock speeds. By maintaining copper’s performance at lower geometries, Applied Materials will help keep performance and power consumption moving even marginally downward as we approach the end of CMOS scaling.